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ISSN 1996-1065 [Online] |
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Volume 2 (1) 2008 |
| Title: | Design Space Exploration Of Network-On-Chip: A System Level Approach |
| Authors: | Rabindra Ku Jena* and Prabhat K. Mahanti |
| Published: | ©IJCIR Vol2 (1) 2008, PP. 17-25 |
| Language: | English |
Abstract:
The growing complexity of system-on-chip is requiring communication resources that can only be
provided by a highly scalable communication infrastructure. This is simplified by Network on Chip
(NoC) architectures. The problem of topological mapping of intellectual properties (IPs) on the tile of a
mesh-based NoC to minimize energy and maximum bandwidth requirement is a NP-hard problem. So,
in this paper, we address the problem of topological mapping of intellectual properties (IPs) on the tile
of a mesh-based NoC to minimize energy and maximum bandwidth requirements using multi-objective
genetic algorithm. We have also considered “many-many” mapping between switch and cores(tiles)
instead of “one-one” mapping. The evaluation performed on three randomly generated benchmarks and
a real application (an M-JPEG encoder) to conform to the efficiency, accuracy and scalability of the
proposed approach.
View full Article
| General Terms: | Design and Modeling |
| Categories and Subject Descriptors: | B.7 [Integrated Circuit]: System Level Synthesis I.2 [Artificial
Intelligence]: Multi-objective genetic algorithm |
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